Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping

Power consumption due to the temperature-dependent leakage current becomes a dominant part of the total power dissipation in systems using nanometer-scale process technology. To obtain the minimum power consumption for different operating conditions, logic synthesis tools are required to take into consideration the leakage power as well as the operating characteristics during the optimization. Conventional logic synthesis flows consider dynamic power only and use an over-simplified cost function in modeling the total power consumption of the logic network. In this paper, we propose a complete model of the total power consumption of the logic network, which includes both the active and standby sub-threshold leakage power, and the operating duty cycle of the applications. We also propose a least leakage vector (LLV) assisted technology mapping algorithm to optimize the total power of the final mapped network. Instead of finding the LLV after the logic network is synthesized and mapped, we use the LLV found in the technology-decomposed network to help in obtaining the lowest total power match during technology mapping. Experimental results on MCNC benchmarks show that on average more than 30% reduction in total power consumption is obtained comparing with the conventional low power technology mapping algorithm.