Low-error configurable truncated multipliers for multiply-accumulate applications

A configurable error-compensation circuit for truncated parallel multipliers is proposed. The proposed circuit is capable of being configured to minimise either the mean error or the mean-square error. Experimental results show that proposed truncated multipliers not only improve error performance f...

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Veröffentlicht in:	Electronics letters 2006-08, Vol.42 (16), p.904-905
Hauptverfasser:	KUANG, S.-R, WANG, J.-P
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Beschreibung
Zusammenfassung:	A configurable error-compensation circuit for truncated parallel multipliers is proposed. The proposed circuit is capable of being configured to minimise either the mean error or the mean-square error. Experimental results show that proposed truncated multipliers not only improve error performance for multiply-accumulate applications but also reduce circuit area, propagation delay, and power consumption with respect to previous solutions.
ISSN:	0013-5194 1350-911X
DOI:	10.1049/el:20061812