Design of cascaded ECL gates with power constraint

A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	Electronics letters 2006-02, Vol.42 (4), p.211-213
Hauptverfasser:	ALIOTO, M, GRASSO, A. D, PALUMBO, G
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!