Design of cascaded ECL gates with power constraint

Design of cascaded ECL gates with power constraint

A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is...

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Veröffentlicht in:Electronics letters 2006-02, Vol.42 (4), p.211-213
Hauptverfasser: ALIOTO, M, GRASSO, A. D, PALUMBO, G
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuit properties
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
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Zusammenfassung:A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20GHz bipolar process are also given.
ISSN:0013-5194
1350-911X
DOI:10.1049/el:20064002