Design of cascaded ECL gates with power constraint
A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is...
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| Veröffentlicht in: | Electronics letters 2006-02, Vol.42 (4), p.211-213 |
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| container_end_page | 213 |
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| container_issue | 4 |
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| container_title | Electronics letters |
| container_volume | 42 |
| creator | ALIOTO, M GRASSO, A. D PALUMBO, G |
| description | A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20GHz bipolar process are also given. |
| doi_str_mv | 10.1049/el:20064002 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_29793833</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>29793833</sourcerecordid><originalsourceid>FETCH-LOGICAL-c294t-d7162d5133589c071e99cf61f88270d20d9af760c3c27380d95831ec67f38c4a3</originalsourceid><addsrcrecordid>eNpFkE1LAzEYhIMoWD9O_oFc9CKr75tkN4k3qfUDCl4UvIXwblJXtrs12VL8925pxdMw8MzADGMXCDcIyt6G9k4AVApAHLAJyhIKi_hxyCYAKIsSrTpmJzl_jVZYqydMPITcLDreR04-k69DzWfTOV_4IWS-aYZPvuo3IXHquzwk33TDGTuKvs3hfK-n7P1x9jZ9LuavTy_T-3lBwqqhqDVWoi5RytJYAo3BWooVRmOEhlpAbX3UFZAkoaUZbWkkBqp0lIaUl6fsate7Sv33OuTBLZtMoW19F_p1dsJqK42UI3i9Ayn1OacQ3So1S59-HILb_uJC6_5-GenLfe12bxuT76jJ_xFdKqsVyl-F0GAZ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>29793833</pqid></control><display><type>article</type><title>Design of cascaded ECL gates with power constraint</title><source>Alma/SFX Local Collection</source><creator>ALIOTO, M ; GRASSO, A. D ; PALUMBO, G</creator><creatorcontrib>ALIOTO, M ; GRASSO, A. D ; PALUMBO, G</creatorcontrib><description>A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20GHz bipolar process are also given.</description><identifier>ISSN: 0013-5194</identifier><identifier>EISSN: 1350-911X</identifier><identifier>DOI: 10.1049/el:20064002</identifier><identifier>CODEN: ELLEAK</identifier><language>eng</language><publisher>London: Institution of Electrical Engineers</publisher><subject>Applied sciences ; Circuit properties ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology</subject><ispartof>Electronics letters, 2006-02, Vol.42 (4), p.211-213</ispartof><rights>2006 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c294t-d7162d5133589c071e99cf61f88270d20d9af760c3c27380d95831ec67f38c4a3</citedby><cites>FETCH-LOGICAL-c294t-d7162d5133589c071e99cf61f88270d20d9af760c3c27380d95831ec67f38c4a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27923,27924</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17549741$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>ALIOTO, M</creatorcontrib><creatorcontrib>GRASSO, A. D</creatorcontrib><creatorcontrib>PALUMBO, G</creatorcontrib><title>Design of cascaded ECL gates with power constraint</title><title>Electronics letters</title><description>A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20GHz bipolar process are also given.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><issn>0013-5194</issn><issn>1350-911X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><recordid>eNpFkE1LAzEYhIMoWD9O_oFc9CKr75tkN4k3qfUDCl4UvIXwblJXtrs12VL8925pxdMw8MzADGMXCDcIyt6G9k4AVApAHLAJyhIKi_hxyCYAKIsSrTpmJzl_jVZYqydMPITcLDreR04-k69DzWfTOV_4IWS-aYZPvuo3IXHquzwk33TDGTuKvs3hfK-n7P1x9jZ9LuavTy_T-3lBwqqhqDVWoi5RytJYAo3BWooVRmOEhlpAbX3UFZAkoaUZbWkkBqp0lIaUl6fsate7Sv33OuTBLZtMoW19F_p1dsJqK42UI3i9Ayn1OacQ3So1S59-HILb_uJC6_5-GenLfe12bxuT76jJ_xFdKqsVyl-F0GAZ</recordid><startdate>20060216</startdate><enddate>20060216</enddate><creator>ALIOTO, M</creator><creator>GRASSO, A. D</creator><creator>PALUMBO, G</creator><general>Institution of Electrical Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>20060216</creationdate><title>Design of cascaded ECL gates with power constraint</title><author>ALIOTO, M ; GRASSO, A. D ; PALUMBO, G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c294t-d7162d5133589c071e99cf61f88270d20d9af760c3c27380d95831ec67f38c4a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>ALIOTO, M</creatorcontrib><creatorcontrib>GRASSO, A. D</creatorcontrib><creatorcontrib>PALUMBO, G</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Electronics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>ALIOTO, M</au><au>GRASSO, A. D</au><au>PALUMBO, G</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design of cascaded ECL gates with power constraint</atitle><jtitle>Electronics letters</jtitle><date>2006-02-16</date><risdate>2006</risdate><volume>42</volume><issue>4</issue><spage>211</spage><epage>213</epage><pages>211-213</pages><issn>0013-5194</issn><eissn>1350-911X</eissn><coden>ELLEAK</coden><abstract>A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20GHz bipolar process are also given.</abstract><cop>London</cop><pub>Institution of Electrical Engineers</pub><doi>10.1049/el:20064002</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0013-5194 |
| ispartof | Electronics letters, 2006-02, Vol.42 (4), p.211-213 |
| issn | 0013-5194 1350-911X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_29793833 |
| source | Alma/SFX Local Collection |
| subjects | Applied sciences Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology |
| title | Design of cascaded ECL gates with power constraint |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T08%3A46%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Design%20of%20cascaded%20ECL%20gates%20with%20power%20constraint&rft.jtitle=Electronics%20letters&rft.au=ALIOTO,%20M&rft.date=2006-02-16&rft.volume=42&rft.issue=4&rft.spage=211&rft.epage=213&rft.pages=211-213&rft.issn=0013-5194&rft.eissn=1350-911X&rft.coden=ELLEAK&rft_id=info:doi/10.1049/el:20064002&rft_dat=%3Cproquest_cross%3E29793833%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=29793833&rft_id=info:pmid/&rfr_iscdi=true |