Fabrication of a nano-scale NAND memory array based on a SONOS Fin-FET cell using e-beam lithography and hydrogen-silsesquioxane resist

Flash memory cells based on a silicon nitride charge trapping layer and multi-gate layout with gate lengths smaller than 48 nm have been investigated as a suitable successor to state-of-the-art non-volatile floating gate memory cells. The NAND memory arrays based on SONOS (silicon-oxide–nitride-oxide–silicon) fin-FET transistors were fabricated using e-beam lithography and hydrogen-silsesquioxane (HSQ) resist. The lithographic procedures to compensate for the topography, positioning, resolution and proximity issues are presented together with electrical characterization. Double fin active areas were structured on top of an optically pre-structured SOI-wafer using an HSQ resist coated in a single step. After etching the silicon fins, an ONO (oxide–nitride-oxide) stack as well as a poly-silicon gate electrode layer were deposited. The structuring of these layers with high topography was accomplished by exposing a double coated HSQ resist film. The first, bottom resist layer acts as planarization layer to obtain a flat surface for the second coating step. After structuring the gate using this resist stack, the device mini-array is completed by a single layer metallization.