Systolic Galois field exponentiation in a multiple-valued logic technique

In this paper, we present two new parallel-in parallel-out systolic array architectures to compute the exponentiation operation for the field GF(2 k ) in a multiple-valued logic (MVL) approach, using the composite field GF((2 2) m ). We compare both circuits with the circuit that use GF(2 k ) as its basis. The proposed circuits require much less amount of chip area, less clock cycles to generate the final output, and are highly regular, thus they are well suited for VLSI.