EEPROM memory stack with scaled down thickness

We studied OAO (oxide-α-Si-oxide) memory stacks of 450–600 Å total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ ralpha-Si floating gates located above the channel edges. The floating gate was 250–400 Å LPCVD amorphous Si or Poly, surrounded by 7...

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Veröffentlicht in:	Microelectronic engineering 2004-04, Vol.72 (1), p.421-425
Hauptverfasser:	Shima Edelstein, Ruth, Cork, Chris, Aloni, Efraim, Vofsy, Nachi, Roizin, Yakov
Format:	Artikel
Sprache:	eng
Schlagworte:	Amorphous Si Applied sciences Breakdown Design. Technologies. Operation analysis. Testing EEPROM Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Multi-bit memory cell Scaling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Storage and reproduction of information Testing, measurement, noise and reliability
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Beschreibung
Zusammenfassung:	We studied OAO (oxide-α-Si-oxide) memory stacks of 450–600 Å total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ ralpha-Si floating gates located above the channel edges. The floating gate was 250–400 Å LPCVD amorphous Si or Poly, surrounded by 70 Å bottom oxide and 125 Å top oxide. Reliability of the new memory stack was evaluated, and the breakdown voltage ( V bd) and charge ( Q bd) of the optimized stack are high enough to use in advanced embedded EEPROM memories, and in particular in memory cells with two isolated poly floating gates.
ISSN:	0167-9317 1873-5568
DOI:	10.1016/j.mee.2004.01.038