Planar, fully ion-implanted InP junction FETs with a nitride-registered gate metallization

Planar, fully ion-implanted InP junction FETs with a nitride-registered gate metallization

A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n/sup +/ source-drain implantation, Be and Be/P p/sup +/ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices f...

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Veröffentlicht in:IEEE electron device letters 1989-02, Vol.10 (2), p.79-81
Hauptverfasser: Boos, J.B., Kruppa, W., Molnar, B.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Electronics
Etching
Exact sciences and technology
Fabrication
Gallium arsenide
Gold
Implants
Indium phosphide
JFETs
Metallization
Ohmic contacts
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transconductance
Transistors
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Beschreibung
Zusammenfassung:A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n/sup +/ source-drain implantation, Be and Be/P p/sup +/ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices fabricated with this approach exhibited a maximum transconductance of 140 mS/mm, which is believed to be the highest reported for InP JFETs.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.32435