Guarded page tables on mips R4600 or an exercise in architecture-dependent micro optimization

Guarded page tables on mips R4600 or an exercise in architecture-dependent micro optimization

Guarded Page Tables implement huge sparsely occupied address spaces efficiently and have the advantages of multi-level tables (tree structure, hierarchy, sharing). We present an implementation guarded page tables on the R4600 processor. The paper describes both the architecture-dependent design proc...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Operating systems review 1996, Vol.30 (1), p.4-15
Hauptverfasser: LIEDTKE, J, ELPHINSTONE, K
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Computer science
control theory
systems
Computer systems and distributed systems. User interface
Exact sciences and technology
Memory and file management (including protection and security)
Memory organisation. Data processing
Software
Software engineering
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Guarded Page Tables implement huge sparsely occupied address spaces efficiently and have the advantages of multi-level tables (tree structure, hierarchy, sharing). We present an implementation guarded page tables on the R4600 processor. The paper describes both the architecture-dependent design process of the algorithms and the resulting tool box.
ISSN:0163-5980
1943-586X
DOI:10.1145/218646.218647