Haar wavelet based processor scheme for image coding with low circuit complexity

A hardware-oriented image coding processing scheme based on the Haar wavelet transform is presented. The procedure computes a variant of the Haar wavelet transform that uses only addition and subtraction operations, after that, an optimized methodology performs the selection and coding of the coefficients, tailored for it with the main aim of attaining the lowest circuit complexity hardware implementation. A selection strategy, which does not require the previous ordering of coefficients, has been used. A non-conventional coding methodology, which uses an optimized combination of techniques adapted to the various groups of coefficients, has been devised for the coding of the selected coefficients leading to a compressed representation of the image and reducing the coding problems inherent in threshold selection. The compression level reached for images of 512 × 512 pixels with 256 grey levels is just over 22:1, (0.4 bits/pixel) with a normalized mean square error, nrmse, of 2–3%, with subjective qualities which can be classified as good. The whole compression circuitry has been described and simulated at HDL level for up to 4 consecutive images, obtaining consistent results. The complete processor (excluding memory) for images of 256 × 256 pixels has been implemented using only one general-purpose low-cost FPGA chip, thus proving the design reliability and its relative simplicity.