High Current Implant Precision Requirements for Sub-65 nm Logic Devices

As CMOS devices shrink they become increasingly sensitive to variations of ion beam angular properties and beam current density. In sub-65 nm devices beam divergence and beam steering variations at levels commonly seen in high current implanters for Source/Drain Extension (SDE) implants could significantly shift device characteristics compromising yield and robustness of manufacturing process. In this paper we review the implant precision requirements for Source/Drain Extension (SDE) formation for sub-65nm node devices. TCAD simulation was used to analyze the effects of beam divergence and steering errors for an on-axis (0 deg ) SDE implant on sub-65 nm NMOS HP devices. Effects of energy contamination introduced along with decelerated low energy ions in p-type SDE implants in PMOS devices is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state-of-the-art ultra-low energy implanters formulated.