65nm Device Characteristics Matching on Single and Batch System Ion Implanter

We examined the process matching between two types of high current implanters; a batch system and a single wafer system. In particular, we investigated the formation by ion implantation of ultra shallow junctions for device characteristics of 65nm generation CMOS logic transistors. Secondary ions mass spectroscopy (SIMS) measurements were performed to profile boron and arsenic. Sample were implanted under various conditions by both types of implanters. The device characteristics were successfully matched using the adjusted implanted conditions using the SIMS profile.