A VLSI layout for a pipelined Dadda multiplier

Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation...

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Veröffentlicht in:	ACM Trans. Comput. Syst.; (United States) 1983-05, Vol.1 (2), p.157-174
Hauptverfasser:	Cappello, Peter R., Steiglitz, Kenneth
Format:	Artikel
Sprache:	eng
Schlagworte:	990200 - Mathematics & Computers DESIGN ELECTRONIC CIRCUITS GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE Hardware INTEGRATED CIRCUITS Logic circuits MICROELECTRONIC CIRCUITS PARALLEL PROCESSING PROGRAMMING Very large scale integration design VLSI system specification and constraints
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