A VLSI layout for a pipelined Dadda multiplier

Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. They analyze the complexity of the resulting design using a VLSI model of computation, showing that it is optimal with respect to both its period and latency. In this sense the design compares favorably with other recent VLSI multiplier designs. 24 references.