A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at rel...

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Veröffentlicht in:IEEE journal of solid-state circuits 1992-07, Vol.27 (7), p.1041-1049
Hauptverfasser: Weston, H.T., Banu, M., Fang, S.-C., Diodato, P.W., Stanik, T.D., Wilford, P.A., Hsu, F.M.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuit properties
Clocks
Differential amplifiers
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuit technology
MOS devices
Optical amplifiers
Optical device fabrication
Silicon
SONET
Standards development
Switching, multiplexing, switched capacity circuits
Very large scale integration
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Zusammenfassung:The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.142600