A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices
We study the effects of gate line edge roughness (LER) on doping profiles of MOSFET transistors using two-dimensional numerical calculation and advanced process simulation. Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found...
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| Veröffentlicht in: | IEEE transactions on electron devices 2004-02, Vol.51 (2), p.228-232 |
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| container_title | IEEE transactions on electron devices |
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| creator | Shiying Xiong Bokor, J. |
| description | We study the effects of gate line edge roughness (LER) on doping profiles of MOSFET transistors using two-dimensional numerical calculation and advanced process simulation. Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found that the transferred roughness has a dominant contribution to the LER effects on device performance. Implantation scattering and diffusion are low-pass filters in the roughness transfer. Low frequency gate LER with 30 nm or larger correlation length (L/sub C/) causes rough S/D-channel junctions, which approximately follow the roughness of gate edges with slight reduction in the RMS roughness value under typical thermal budget. Implantation scattering and diffusion smooth off a major part of the high frequency junction roughness induced by gate LER with 5 nm or smaller L/sub C/. In addition, the average lateral diffusion length is enhanced when this high-frequency roughness is present. |
| doi_str_mv | 10.1109/TED.2003.821563 |
| format | Article |
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Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found that the transferred roughness has a dominant contribution to the LER effects on device performance. Implantation scattering and diffusion are low-pass filters in the roughness transfer. Low frequency gate LER with 30 nm or larger correlation length (L/sub C/) causes rough S/D-channel junctions, which approximately follow the roughness of gate edges with slight reduction in the RMS roughness value under typical thermal budget. Implantation scattering and diffusion smooth off a major part of the high frequency junction roughness induced by gate LER with 5 nm or smaller L/sub C/. In addition, the average lateral diffusion length is enhanced when this high-frequency roughness is present.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2003.821563</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Computer simulation ; Devices ; Diffusion ; Doping ; Gates ; Implantation ; Low-pass filters ; MOSFETs ; Roughness ; Semiconductor device modeling ; Semiconductor process modeling</subject><ispartof>IEEE transactions on electron devices, 2004-02, Vol.51 (2), p.228-232</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found that the transferred roughness has a dominant contribution to the LER effects on device performance. Implantation scattering and diffusion are low-pass filters in the roughness transfer. Low frequency gate LER with 30 nm or larger correlation length (L/sub C/) causes rough S/D-channel junctions, which approximately follow the roughness of gate edges with slight reduction in the RMS roughness value under typical thermal budget. Implantation scattering and diffusion smooth off a major part of the high frequency junction roughness induced by gate LER with 5 nm or smaller L/sub C/. In addition, the average lateral diffusion length is enhanced when this high-frequency roughness is present.</description><subject>Computer simulation</subject><subject>Devices</subject><subject>Diffusion</subject><subject>Doping</subject><subject>Gates</subject><subject>Implantation</subject><subject>Low-pass filters</subject><subject>MOSFETs</subject><subject>Roughness</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor process modeling</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkc1LAzEQxYMoWKtnD16CBz1tm6_NJsdSP0HpQT2HbHa2jWw3dbMr9L83pYLgQU_DML83vMdD6JySCaVET19vbyaMED5RjOaSH6ARzfMi01LIQzQihKpMc8WP0UmM72mVQrAR8jMc_XpobO9Di2M_VFscary0PeDGt4ChWgLuwrBctRAjhroG10ec4CpsfLvEmy7UvoG4k8VV6PrMrWzbQoOfFy93t6-4gk_vIJ6io9o2Ec6-5xi9pev8IXta3D_OZ0-ZE0L2WWFlVdZM81JTUkLuygqAOcErqAotC-vKmtqilIpKkoILSVgyZW0KSkpS8jG63v9Nxj4GiL1Z--igaWwLYYhGp-iKFlQn8upPkmnCmSjI_6DKJVNEJfDyF_gehq5NcY1SghKp8zxB0z3kuhBjB7XZdH5tu62hxOyqNKlKs6vS7KtMiou9wgPAD80kkznlXzXymfQ</recordid><startdate>20040201</startdate><enddate>20040201</enddate><creator>Shiying Xiong</creator><creator>Bokor, J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found that the transferred roughness has a dominant contribution to the LER effects on device performance. Implantation scattering and diffusion are low-pass filters in the roughness transfer. Low frequency gate LER with 30 nm or larger correlation length (L/sub C/) causes rough S/D-channel junctions, which approximately follow the roughness of gate edges with slight reduction in the RMS roughness value under typical thermal budget. Implantation scattering and diffusion smooth off a major part of the high frequency junction roughness induced by gate LER with 5 nm or smaller L/sub C/. In addition, the average lateral diffusion length is enhanced when this high-frequency roughness is present.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2003.821563</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Computer simulation Devices Diffusion Doping Gates Implantation Low-pass filters MOSFETs Roughness Semiconductor device modeling Semiconductor process modeling |
| title | A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices |
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