A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices

We study the effects of gate line edge roughness (LER) on doping profiles of MOSFET transistors using two-dimensional numerical calculation and advanced process simulation. Gate LER transfers the roughness to doping profiles self-aligned to gate edges such as source/drain (S/D) extensions. We found that the transferred roughness has a dominant contribution to the LER effects on device performance. Implantation scattering and diffusion are low-pass filters in the roughness transfer. Low frequency gate LER with 30 nm or larger correlation length (L/sub C/) causes rough S/D-channel junctions, which approximately follow the roughness of gate edges with slight reduction in the RMS roughness value under typical thermal budget. Implantation scattering and diffusion smooth off a major part of the high frequency junction roughness induced by gate LER with 5 nm or smaller L/sub C/. In addition, the average lateral diffusion length is enhanced when this high-frequency roughness is present.