Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si(1-x)Ge(x) source/drain

P-channel MOS transistors with raised Si(1-x)Ge(x ) and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si(1-x)Ge(x) and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si(1-x)Ge(x) S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R(SD)), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R(SD) of devices with Si(1-x)Ge(x) raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g(m)) at an effective channel length of 0.16 mum. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si(1-x)Ge(x) S/D structure very attractive for future sub-0.1 mum p-channel MOS transistors