Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-mum SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process.