Low-power Viterbi decoder for CDMA mobile terminals

An efficient state-sequential very large scale integration (VLSI) architecture and low-power design methodologies ranging from the system-level to the layout-level are presented for a large-constraint-length Viterbi decoder for code division multiple access (CDMA) digital cellular/personal communica...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1998-03, Vol.33 (3), p.473-482
Hauptverfasser:	Kang, I., Willson, A.N.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis CMOS technology Decoding Design methodology Fabrication Multiaccess communication Personal communication networks Prototypes Very large scale integration Viterbi algorithm
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