A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept,...

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Veröffentlicht in:IEEE transactions on electron devices 1996-09, Vol.43 (9), p.1539-1546
Hauptverfasser: van der Wel, W., Koster, R., Jansen, S.C.L., Ahlrichs, F.W., Baltus, P.G.M., Kant, G.W.
Format: Artikel
Sprache:eng
Schlagworte:
BiCMOS integrated circuits
Bipolar transistors
Cutoff frequency
Energy consumption
Etching
Isolation technology
Low-noise amplifiers
MOS devices
Parasitic capacitance
Substrates
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Zusammenfassung:A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 /spl mu/m-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.535347