Synergistic Processing in Cell's Multicore Architecture
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level para...
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Veröffentlicht in: | IEEE MICRO 2006-03, Vol.26 (2), p.10-24 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. The streamlined architecture provides an efficient multithreaded execution environment for both scalar and SIMD threads and represents a reaffirmation of the RISC principles of combining leading edge architecture and compiler optimizations. These design decisions have enabled the Cell BE to deliver unprecedented supercomputer-class compute power for consumer applications |
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ISSN: | 0272-1732 1937-4143 |
DOI: | 10.1109/MM.2006.41 |