Effects of gate sidewall recess on Al0.2Ga0.8As/ In0.15Ga0.85As PHEMTs by citric-based selective etchant

In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al^sub 0.2^Ga^sub 0.8^As/ In^sub 0.15^Ga^sub 0.85^As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (> 250) for GaAs/Al^sub 0.2^Ga^sub 0.8^As or In^sub 0.15^Ga^sub 0.85^As/Al^sub 0.2^G^sub 0.8^ As interfaces. After sidewall recess, a revealed cavity will exist between the In^sub 0.15^Ga^sub 0.85^As layers and gate metals. Devices with 1 × 100μm^sup 2^ exhibit a very low gate leakage current of 2.4μA/mm even at V^sub GD^ = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage can be achieved.[PUBLICATION ABSTRACT]