Exploiting instruction- and data-level parallelism
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
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| Veröffentlicht in: | IEEE MICRO 1997-09, Vol.17 (5), p.20-27 |
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| container_end_page | 27 |
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| container_issue | 5 |
| container_start_page | 20 |
| container_title | IEEE MICRO |
| container_volume | 17 |
| creator | Espasa, R. Valero, M. |
| description | Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications. |
| doi_str_mv | 10.1109/40.621210 |
| format | Article |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0272-1732 |
| ispartof | IEEE MICRO, 1997-09, Vol.17 (5), p.20-27 |
| issn | 0272-1732 1937-4143 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28818008 |
| source | IEEE Electronic Library (IEL) |
| subjects | Arquitectura de computadors Clocks Computer aided instruction Computer architecture Computer science Delay Informàtica Multithreading Out of order Parallel processing Parallel processing (Electronic computers) Performance evaluation Processament en paral·lel (Ordinadors) Random access memory Registers Vector processor systems Wire Àrees temàtiques de la UPC |
| title | Exploiting instruction- and data-level parallelism |
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