Exploiting instruction- and data-level parallelism

Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE MICRO 1997-09, Vol.17 (5), p.20-27
Hauptverfasser:	Espasa, R., Valero, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Arquitectura de computadors Clocks Computer aided instruction Computer architecture Computer science Delay Informàtica Multithreading Out of order Parallel processing Parallel processing (Electronic computers) Performance evaluation Processament en paral·lel (Ordinadors) Random access memory Registers Vector processor systems Wire Àrees temàtiques de la UPC
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Beschreibung
Zusammenfassung:	Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
ISSN:	0272-1732 1937-4143
DOI:	10.1109/40.621210