Using Coincident Optical Pulses for Parallel Memory Addressing

A novel memory structure is proposed which allows parallel access to be realized in a multiprocessor environment. The system distributes the address-decoding circuitry to each of the requesting units on a common bus, thereby eliminating the bottleneck of centralized decoding; it then allows parallel fetches of memory data, with a level of parallelism that is limited only by the ratios of optical to electronic bus bandwidths and the dimensionality of the memory. The primary application of the system is to two-dimensional, multiported memory modules. (O.C.)