A new and improved borderless contact (BLC) structure for high-performance Ti-salicide in sub-quarter micron CMOS devices

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO/sub x/N/sub y/ film to act as the selective etching stop layer and the additional n/sup +/ and p/sup +/ source-drain double implant structure (DIS) are employed in the studied device. The additional n/sup +/ and p/sup +/ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration.