Fault-secure parity prediction Booth multipliers

Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding.

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE design & test of computers 1999-07, Vol.16 (3), p.90-101
Hauptverfasser:	Nicolaidis, M., Duarte, R.O.
Format:	Artikel
Sprache:	eng
Schlagworte:	Arithmetic Booths Circuit topology Compatibility Complexity theory Data paths Decoding Design engineering Digital arithmetic Dividers Engineering Sciences Equations Hardware Micro and nanotechnologies Microelectronics Multipliers Parity Routing System testing
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Beschreibung
Zusammenfassung:	Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding.
ISSN:	0740-7475 2168-2356 1558-1918
DOI:	10.1109/54.785842