A video signal processor for motion-compensated field-rate upconversion in consumer television

A video signal processor for motion-compensated field-rate upconversion in consumer television

An IC for 100-Hz television has been realized implementing motion estimation and compensation algorithms for high-quality upconversion and a judder-free motion portrayal of movie material. The four embedded video signal processors on this IC provide a processing power of 10 giga-operation per second...

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Veröffentlicht in:IEEE journal of solid-state circuits 1996-11, Vol.31 (11), p.1762-1769
Hauptverfasser: Lippens, P., De Loore, B., de Haan, G., Eeckhout, P., Huijgen, H., Loning, A., McSweeney, B., Verstraeien, M., Pahn, B., Kettenis, J.
Format: Artikel
Sprache:eng
Schlagworte:
Bandwidth
Motion estimation
Motion pictures
Random access memory
Signal processing
Signal processing algorithms
Signal synthesis
Technological innovation
Testing
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Beschreibung
Zusammenfassung:An IC for 100-Hz television has been realized implementing motion estimation and compensation algorithms for high-quality upconversion and a judder-free motion portrayal of movie material. The four embedded video signal processors on this IC provide a processing power of 10 giga-operation per second (GOPS). Their architecture was generated from an algorithm description using behavioral synthesis. The required 25-Gb/s memory bandwidth was realized by embedding 24 single/dual port SRAM/DRAM instances. The test approach includes full scan, boundary scan, functional testing, built-in-self-test, and IDDq-test. The so-called "Natural Motion" feature implemented by this IC was demonstrated at the IFA'95 and received the European Video Innovation Award 95-96.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1996.542321