Synthesis of fully testable circuits from BDDs
We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inve...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2004-03, Vol.23 (3), p.440-443 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Drechsler, R. Junhao Shi Fey, G. |
| description | We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique. |
| doi_str_mv | 10.1109/TCAD.2004.823342 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28676611</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1269866</ieee_id><sourcerecordid>2427392731</sourcerecordid><originalsourceid>FETCH-LOGICAL-c352t-97c657d3eb71263e32c15de2a964df5703ceae42dbfaedff2331e73e3a5e941a3</originalsourceid><addsrcrecordid>eNp90LtPwzAQBnALgUR57EgsEQNiSfDZ8WssLS-pEgNlttzkLFKlTbGTof89roKExMB0y-9O332EXAEtAKi5X86m84JRWhaacV6yIzIBw1VegoBjMqFM6ZxSRU_JWYxrSqEUzExI8b7f9p8Ym5h1PvND2-6zHmPvVi1mVROqoelj5kO3yR7m83hBTrxrI17-zHPy8fS4nL3ki7fn19l0kVdcsD43qpJC1RxXCpjkyFkFokbmjCxrLxTlFTosWb3yDmvvU2JAlZwTaEpw_Jzcjnd3ofsaUh67aWKFbeu22A3RMi2VlAAJ3v0LQSrgFARjid78oetuCNv0htWaa6MFiIToiKrQxRjQ211oNi7sLVB7KNoeiraHou1YdFq5HlcaRPzlTBotJf8GRbZ3mw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>883898515</pqid></control><display><type>article</type><title>Synthesis of fully testable circuits from BDDs</title><source>IEEE Electronic Library (IEL)</source><creator>Drechsler, R. ; Junhao Shi ; Fey, G.</creator><creatorcontrib>Drechsler, R. ; Junhao Shi ; Fey, G.</creatorcontrib><description>We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2004.823342</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Binary decision diagrams ; Boolean functions ; Circuit faults ; Circuit synthesis ; Circuit testing ; Circuits ; Computer aided design ; Data structures ; Design engineering ; Faults ; Inverters ; Logic circuits ; Logic design ; Mathematical analysis ; Mathematical models ; Redundancy ; Synthesis</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2004-03, Vol.23 (3), p.440-443</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c352t-97c657d3eb71263e32c15de2a964df5703ceae42dbfaedff2331e73e3a5e941a3</citedby><cites>FETCH-LOGICAL-c352t-97c657d3eb71263e32c15de2a964df5703ceae42dbfaedff2331e73e3a5e941a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1269866$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1269866$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Drechsler, R.</creatorcontrib><creatorcontrib>Junhao Shi</creatorcontrib><creatorcontrib>Fey, G.</creatorcontrib><title>Synthesis of fully testable circuits from BDDs</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.</description><subject>Algorithms</subject><subject>Binary decision diagrams</subject><subject>Boolean functions</subject><subject>Circuit faults</subject><subject>Circuit synthesis</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>Computer aided design</subject><subject>Data structures</subject><subject>Design engineering</subject><subject>Faults</subject><subject>Inverters</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>Redundancy</subject><subject>Synthesis</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp90LtPwzAQBnALgUR57EgsEQNiSfDZ8WssLS-pEgNlttzkLFKlTbGTof89roKExMB0y-9O332EXAEtAKi5X86m84JRWhaacV6yIzIBw1VegoBjMqFM6ZxSRU_JWYxrSqEUzExI8b7f9p8Ym5h1PvND2-6zHmPvVi1mVROqoelj5kO3yR7m83hBTrxrI17-zHPy8fS4nL3ki7fn19l0kVdcsD43qpJC1RxXCpjkyFkFokbmjCxrLxTlFTosWb3yDmvvU2JAlZwTaEpw_Jzcjnd3ofsaUh67aWKFbeu22A3RMi2VlAAJ3v0LQSrgFARjid78oetuCNv0htWaa6MFiIToiKrQxRjQ211oNi7sLVB7KNoeiraHou1YdFq5HlcaRPzlTBotJf8GRbZ3mw</recordid><startdate>20040301</startdate><enddate>20040301</enddate><creator>Drechsler, R.</creator><creator>Junhao Shi</creator><creator>Fey, G.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope><scope>7TB</scope></search><sort><creationdate>20040301</creationdate><title>Synthesis of fully testable circuits from BDDs</title><author>Drechsler, R. ; Junhao Shi ; Fey, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c352t-97c657d3eb71263e32c15de2a964df5703ceae42dbfaedff2331e73e3a5e941a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Algorithms</topic><topic>Binary decision diagrams</topic><topic>Boolean functions</topic><topic>Circuit faults</topic><topic>Circuit synthesis</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>Computer aided design</topic><topic>Data structures</topic><topic>Design engineering</topic><topic>Faults</topic><topic>Inverters</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>Redundancy</topic><topic>Synthesis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Drechsler, R.</creatorcontrib><creatorcontrib>Junhao Shi</creatorcontrib><creatorcontrib>Fey, G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Drechsler, R.</au><au>Junhao Shi</au><au>Fey, G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Synthesis of fully testable circuits from BDDs</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2004-03-01</date><risdate>2004</risdate><volume>23</volume><issue>3</issue><spage>440</spage><epage>443</epage><pages>440-443</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2004.823342</doi><tpages>4</tpages></addata></record> |
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| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2004-03, Vol.23 (3), p.440-443 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Binary decision diagrams Boolean functions Circuit faults Circuit synthesis Circuit testing Circuits Computer aided design Data structures Design engineering Faults Inverters Logic circuits Logic design Mathematical analysis Mathematical models Redundancy Synthesis |
| title | Synthesis of fully testable circuits from BDDs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T11%3A31%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Synthesis%20of%20fully%20testable%20circuits%20from%20BDDs&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Drechsler,%20R.&rft.date=2004-03-01&rft.volume=23&rft.issue=3&rft.spage=440&rft.epage=443&rft.pages=440-443&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/TCAD.2004.823342&rft_dat=%3Cproquest_RIE%3E2427392731%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=883898515&rft_id=info:pmid/&rft_ieee_id=1269866&rfr_iscdi=true |