Synthesis of fully testable circuits from BDDs

Synthesis of fully testable circuits from BDDs

We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inve...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2004-03, Vol.23 (3), p.440-443
Hauptverfasser: Drechsler, R., Junhao Shi, Fey, G.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
Binary decision diagrams
Boolean functions
Circuit faults
Circuit synthesis
Circuit testing
Circuits
Computer aided design
Data structures
Design engineering
Faults
Inverters
Logic circuits
Logic design
Mathematical analysis
Mathematical models
Redundancy
Synthesis
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Beschreibung
Zusammenfassung:We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2004.823342