A tabular method for guard strengthening, symmetrization, and operator reduction for Martin's asynchronous design methodology
We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and...
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| Veröffentlicht in: | IEEE transactions on computers 1997-09, Vol.46 (9), p.1050-1054 |
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| container_end_page | 1054 |
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| container_issue | 9 |
| container_start_page | 1050 |
| container_title | IEEE transactions on computers |
| container_volume | 46 |
| creator | Tabrizi, N. Liebelt, M.J. Eshraghian, K. |
| description | We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation. |
| doi_str_mv | 10.1109/12.620487 |
| format | Article |
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The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation.</description><subject>Applied sciences</subject><subject>Asynchronous circuits</subject><subject>Circuit synthesis</subject><subject>Clocks</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Driver circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Logic design</subject><subject>Production</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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| ispartof | IEEE transactions on computers, 1997-09, Vol.46 (9), p.1050-1054 |
| issn | 0018-9340 1557-9956 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Asynchronous circuits Circuit synthesis Clocks Delay Design methodology Design. Technologies. Operation analysis. Testing Driver circuits Electronics Exact sciences and technology Integrated circuits Logic design Production Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sequential circuits Signal synthesis |
| title | A tabular method for guard strengthening, symmetrization, and operator reduction for Martin's asynchronous design methodology |
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