A tabular method for guard strengthening, symmetrization, and operator reduction for Martin's asynchronous design methodology

We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and...

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Veröffentlicht in:	IEEE transactions on computers 1997-09, Vol.46 (9), p.1050-1054
Hauptverfasser:	Tabrizi, N., Liebelt, M.J., Eshraghian, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Asynchronous circuits Circuit synthesis Clocks Delay Design methodology Design. Technologies. Operation analysis. Testing Driver circuits Electronics Exact sciences and technology Integrated circuits Logic design Production Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sequential circuits Signal synthesis
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Beschreibung
Zusammenfassung:	We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation.
ISSN:	0018-9340 1557-9956
DOI:	10.1109/12.620487