Itanium[trademark] Processor system bus design

Itanium[trademark] Processor system bus design

This paper presents the design of the Itanium[trademark] Processors system bus interface achieving a peak data bandwidth of 2.1 GB/s in a glueless four-way multiprocessing System. A source-synchronous data bus with differential strobes enables this high bandwidth. Topics covered in this paper includ...

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Veröffentlicht in:IEEE journal of solid-state circuits 2001-10, Vol.36 (10), p.1565-1573
Hauptverfasser: Ilkbahar, A, Venkataraman, S, Muljono, H
Format: Artikel
Sprache:eng
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Zusammenfassung:This paper presents the design of the Itanium[trademark] Processors system bus interface achieving a peak data bandwidth of 2.1 GB/s in a glueless four-way multiprocessing System. A source-synchronous data bus with differential strobes enables this high bandwidth. Topics covered in this paper include optimization technique for the system topology, CPU package, signaling protocol, and I/O circuits. Highly accurate modeling and validation methodologies enable a good correlation of experimental results with simulation data.
ISSN:0018-9200
DOI:10.1109/4.953486