SAVIA, an advanced multi-layer parallel lamination technique for high density, high performance printed circuit boards

Purpose - To review a newly developed PCB fabrication process based on a parallel lamination technique.Design methodology approach - This paper has been written to introduce the SAVIA process, a new parallel lamination technique for PCB fabrication. The basic concept of the SAVIA process has been de...

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Veröffentlicht in:Circuit world 2005-09, Vol.31 (3), p.17-20
Hauptverfasser: Kim, Taehoon, Mok, Jee-Soo, Song, Chang-Kyu, Park, Jun-Heyoung, Kim, Kyung-O, Sun, Ben, Min, Byung-Youl
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Sprache:eng
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Zusammenfassung:Purpose - To review a newly developed PCB fabrication process based on a parallel lamination technique.Design methodology approach - This paper has been written to introduce the SAVIA process, a new parallel lamination technique for PCB fabrication. The basic concept of the SAVIA process has been described along with the individual process steps and the reliability issues. The advantages of SAVIA process have been also discussed in both economical and technological aspects.Findings - It was found that the parallel lamination technique, a key process for SAVIA, was not only highly flexible and reliable but also a cost-effective fabrication method for high performance PCB. With the SAVIA process, manufacturing lead-times can be substantially reduced due to the nature of the parallel processing. It was also confirmed that a highly reliable metal alloy interconnection was created between the core and the adhesive layers during the lamination process. The formed metal alloy contacts showed excellent electrical and physical characteristics. The between layers was precise.Originality value - The value of this paper is to introduce a novel PCB fabrication process based on a parallel lamination technique that is superior to conventional build-up processes from both technological and economical viewpoints. By applying a parallel lamination technique, it is expected that fabrication costs can be lowered due to reductions in manufacturing lead-time.
ISSN:0305-6120
1758-602X
0305-6120
DOI:10.1108/03056120510585027