SEU critical charge and sensitive area in a submicron CMOS technology

SEU critical charge and sensitive area in a submicron CMOS technology

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

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Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on Nuclear Science 1997-12, Vol.44 (6), p.2266-2273
Hauptverfasser: Detcheverry, C., Dachs, C., Lorfevre, E., Sudre, C., Bruguier, G., Palau, J.M., Gasiot, J., Ecoffet, R.
Format: Artikel
Sprache:eng
Schlagworte:
CHARGE COLLECTION
Circuit simulation
CMOS technology
ERRORS
HEAVY IONS
INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS
Inverters
PHYSICAL RADIATION EFFECTS
Random access memory
SCALING LAWS
Semiconductor process modeling
SEMICONDUCTOR STORAGE DEVICES
Single event upset
Space technology
SPICE
Switches
Voltage
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Beschreibung
Zusammenfassung:This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.
ISSN:0018-9499
1558-1578
DOI:10.1109/23.659045