SEU design considerations for MESFETs on LT GaAs

SEU design considerations for MESFETs on LT GaAs

Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII(R) process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU...

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Veröffentlicht in:IEEE transactions on nuclear science 1997-12, Vol.44 (6), p.2282-2289
Hauptverfasser: Weatherford, T.R., Radice, R., Eskins, D., Devers, J., Fouts, D.J., Marshall, P.W., Marshall, C.J., Dietrich, H., Twigg, M., Milano, R.
Format: Artikel
Sprache:eng
Schlagworte:
FETs
Gallium arsenide
Implants
Laboratories
Logic devices
MESFETs
Molecular beam epitaxial growth
Semiconductor device modeling
Semiconductor process modeling
Single event upset
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Beschreibung
Zusammenfassung:Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII(R) process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined.
ISSN:0018-9499
1558-1578
DOI:10.1109/23.659047