Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes

Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes

A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running st...

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Veröffentlicht in:IEEE transactions on signal processing 1995-01, Vol.43 (1), p.286-295
Hauptverfasser: Gevorkian, D.Z., Egiazarian, K.O., Agaian, S.S., Astola, J.T., Vainio, O.
Format: Artikel
Sprache:eng
Schlagworte:
Adaptive filters
Applied sciences
Computer architecture
Concurrent computing
Detection, estimation, filtering, equalization, prediction
Digital filters
Exact sciences and technology
Filtering
Information, signal and communications theory
Nonlinear filters
Parallel algorithms
Signal and communications theory
Signal processing algorithms
Signal, noise
Statistics
Telecommunications and information theory
Very large scale integration
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Beschreibung
Zusammenfassung:A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated.< >
ISSN:1053-587X
1941-0476
DOI:10.1109/78.365308