Polycrystalline silicon thin film transistors fabricated at reduced thermal budgets by utilizing fluorinated gate oxidation

Polycrystalline silicon thin film transistors have been fabricated at reduced gate oxidation thermal budgets by utilizing NF/sub 3/-enhanced dry oxidation. Good performance TFTs with effective electron mobility values as high as 38 cm/sup 2//V.sec, threshold voltage values near zero, ON/OFF current ratios of up to 5/spl times/10/sup 7/ and subthreshold slopes of 0.3 V/dec have been fabricated at an oxidation temperature of 800/spl deg/C. Stable devices at an electrical stressing field of 3 MV/cm were demonstrated. Thermal gate oxide TFTs have also been fabricated at a maximum temperature of 650/spl deg/C. The effect of hydrogen plasma passivation was found to depend on process conditions and was correlated with the amount of fluorine in the area near the Si-SiO/sub 2/ interface. Passivation at low power was always beneficial. Passivation at high power was highly beneficial for a limited amount of interfacial fluorine, but less beneficial or even detrimental when a large fluorine amount in the near interface area was present.