A poly-framed LDD sub-half-micrometer CMOS technology
A novel LDD spacer technology that uses disposable silicon nitride spacers on a sacrificial polysilicon frame has been developed for a sub-half-micrometer CMOS technology. An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the...
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| Veröffentlicht in: | IEEE electron device letters 1990-11, Vol.11 (11), p.529-531 |
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| container_end_page | 531 |
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| container_issue | 11 |
| container_start_page | 529 |
| container_title | IEEE electron device letters |
| container_volume | 11 |
| creator | Pfiester, J.R. Crain, N. Lin, J.-H. Gunderson, C.D. Kaushik, V. |
| description | A novel LDD spacer technology that uses disposable silicon nitride spacers on a sacrificial polysilicon frame has been developed for a sub-half-micrometer CMOS technology. An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the effect of substrate bias on the drain junction leakage caused by sidewall spacer formation is eliminated. The DC hot-carrier lifetime for the 0.3- mu m-channel-length poly-framed LDD NMOS devices, defined as the time associated with a 10% shift in peak transconductance, is in excess of 10 years for a power supply voltage of 3.3 V.< > |
| doi_str_mv | 10.1109/55.63022 |
| format | Article |
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An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the effect of substrate bias on the drain junction leakage caused by sidewall spacer formation is eliminated. The DC hot-carrier lifetime for the 0.3- mu m-channel-length poly-framed LDD NMOS devices, defined as the time associated with a 10% shift in peak transconductance, is in excess of 10 years for a power supply voltage of 3.3 V.< ></description><subject>Annealing</subject><subject>Applied sciences</subject><subject>Boron</subject><subject>CMOS technology</subject><subject>Diodes</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hot carriers</subject><subject>Implants</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>MOSFET circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Space technology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pfiester, J.R.</creatorcontrib><creatorcontrib>Crain, N.</creatorcontrib><creatorcontrib>Lin, J.-H.</creatorcontrib><creatorcontrib>Gunderson, C.D.</creatorcontrib><creatorcontrib>Kaushik, V.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Ceramic Abstracts</collection><collection>Materials Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pfiester, J.R.</au><au>Crain, N.</au><au>Lin, J.-H.</au><au>Gunderson, C.D.</au><au>Kaushik, V.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A poly-framed LDD sub-half-micrometer CMOS technology</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>1990-11-01</date><risdate>1990</risdate><volume>11</volume><issue>11</issue><spage>529</spage><epage>531</epage><pages>529-531</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>A novel LDD spacer technology that uses disposable silicon nitride spacers on a sacrificial polysilicon frame has been developed for a sub-half-micrometer CMOS technology. An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the effect of substrate bias on the drain junction leakage caused by sidewall spacer formation is eliminated. The DC hot-carrier lifetime for the 0.3- mu m-channel-length poly-framed LDD NMOS devices, defined as the time associated with a 10% shift in peak transconductance, is in excess of 10 years for a power supply voltage of 3.3 V.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/55.63022</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 1990-11, Vol.11 (11), p.529-531 |
| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Annealing Applied sciences Boron CMOS technology Diodes Electronics Exact sciences and technology Hot carriers Implants Microelectronic fabrication (materials and surfaces technology) MOSFET circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Space technology |
| title | A poly-framed LDD sub-half-micrometer CMOS technology |
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