A poly-framed LDD sub-half-micrometer CMOS technology

A novel LDD spacer technology that uses disposable silicon nitride spacers on a sacrificial polysilicon frame has been developed for a sub-half-micrometer CMOS technology. An improvement in short-channel behavior is achieved due to a reduction in lateral LDD n/sup -/ and p/sup -/ diffusion, and the effect of substrate bias on the drain junction leakage caused by sidewall spacer formation is eliminated. The DC hot-carrier lifetime for the 0.3- mu m-channel-length poly-framed LDD NMOS devices, defined as the time associated with a 10% shift in peak transconductance, is in excess of 10 years for a power supply voltage of 3.3 V.< >