An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1995-11, Vol.30 (11), p.1165-1173, Article 1165
Hauptverfasser:	Sakata, T., Horiguchi, M., Sekiguchi, T., Ueda, S., Tanaka, H., Yamasaki, E., Nakagome, Y., Aoki, M., Kaga, T., Ohkura, M., Nagai, R., Murai, F., Tanaka, T., Iijima, S., Yokoyama, N., Gotoh, Y., Shoji, I., Kisu, T., Yamashita, H., Nishida, T., Takeda, E.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits Clocks Delay Frequency Graphics HDTV Pipelines Random access memory Timing Wiring
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