An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture
A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1995-11, Vol.30 (11), p.1165-1173, Article 1165 |
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| container_end_page | 1173 |
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| container_issue | 11 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 30 |
| creator | Sakata, T. Horiguchi, M. Sekiguchi, T. Ueda, S. Tanaka, H. Yamasaki, E. Nakagome, Y. Aoki, M. Kaga, T. Ohkura, M. Nagai, R. Murai, F. Tanaka, T. Iijima, S. Yokoyama, N. Gotoh, Y. Shoji, I. Kisu, T. Yamashita, H. Nishida, T. Takeda, E. |
| description | A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-/spl mu/m CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply. |
| doi_str_mv | 10.1109/4.475703 |
| format | Article |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuits Clocks Delay Frequency Graphics HDTV Pipelines Random access memory Timing Wiring |
| title | An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture |
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