A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/ / poly gate formed by BF(2) ion implanted compensation of in situ phosphorus (n/ /) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/ /- and p/ /-doped WSi(x)-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/kappa/ Al(2)O(3) and HfO(2) dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.