Intermetal dielectric-induced N-field device failure in double-level-metal CMOS process

Intermetal dielectric-induced N-field device failure in double-level-metal CMOS process

In double-level-metal CMOS production processes, the silicate-based spin-on-glass (SOG) planarization scheme, even without a nitride passivation layer, is observed to cause N-field device failure which appears to be due to positive charges trapped in the SOG sandwich layer. Ultraviolet (UV) exposure...

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Veröffentlicht in:IEEE electron device letters 1992-08, Vol.13 (8), p.405-407
Hauptverfasser: Kuo, H.H., Lin, K.M., Liu, C.M., Tsai, R., Lin, M.-S., Yoo, C.S.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
CMOS process
Degradation
Design. Technologies. Operation analysis. Testing
Dielectric devices
Dielectric measurements
Diodes
Electric breakdown
Electronics
Exact sciences and technology
Integrated circuits
Passivation
Planarization
Production
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Testing
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Beschreibung
Zusammenfassung:In double-level-metal CMOS production processes, the silicate-based spin-on-glass (SOG) planarization scheme, even without a nitride passivation layer, is observed to cause N-field device failure which appears to be due to positive charges trapped in the SOG sandwich layer. Ultraviolet (UV) exposure and backbias are found to be able to eliminate the field and active device leakage. A mechanism is proposed to explain the formation of the positive charges and the UV curing phenomena.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.192773