An imager with built-in image-velocity computation capability

An imager with built-in image-velocity computation capability

An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using 3- mu m-CMOS technology is described. Experimental results show that a computational error of less than 20...

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Veröffentlicht in:IEEE transactions on circuits and systems for video technology 1992-09, Vol.2 (3), p.306-312
Hauptverfasser: Chong, C.P., Salama, C.A.T., Smith, K.C.
Format: Artikel
Sprache:eng
Schlagworte:
Delay lines
Error correction
Fabrication
Image analysis
Image edge detection
Image segmentation
Propagation delay
Signal design
Silicon
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Zusammenfassung:An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using 3- mu m-CMOS technology is described. Experimental results show that a computational error of less than 20% can be achieved using available fabrication technology. This figure can be reduced by using larger arrays and better implementations of delay gates.< >
ISSN:1051-8215
1558-2205
DOI:10.1109/76.157162