An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequenc...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1996-12, Vol.31 (12), p.1846-1853
Hauptverfasser:	Venes, A.G.W., van-de-Plassche, R.J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog-digital conversion Bandwidth Clocks CMOS technology Data preprocessing Frequency conversion Interpolation Power dissipation Signal to noise ratio Voltage
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container_end_page	1853
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container_title	IEEE journal of solid-state circuits
container_volume	31
creator	Venes, A.G.W. van-de-Plassche, R.J.
description	An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.
doi_str_mv	10.1109/4.545804
format	Article
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The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.</description><subject>Analog-digital conversion</subject><subject>Bandwidth</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Data preprocessing</subject><subject>Frequency conversion</subject><subject>Interpolation</subject><subject>Power dissipation</subject><subject>Signal to noise ratio</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNo9kL1PwzAQxS0EEqUgMTN5Qgy4tWM7sceqfBSpVQdAMBE59oUG0qS1UxD89SRKxfR0d79373QInTM6YozqsRhJIRUVB2jApFSEJfz1EA0oZYroiNJjdBLCR1sKodgAvU0qrChZzH6vO12_tEIyPF0sH3Fel66o3vFkfINtXX2Bb8Dj76JZYVeExhfZrgGHG2_sJzGVI6vWgDceNr62EELrPUVHuSkDnO11iJ7vbp-mMzJf3j9MJ3Nio0Q2hFklu-u1yVicxFHkOI9p14GM28iZhEVxrkWS5NoBGCWVcJbqLHfa5TzhQ3TZ722jtzsITbougoWyNBXUu5BGimsu4w686kHr6xA85OnGF2vjf1JG0y4wFWn_wBa96NECAP6x_fAPY3toPQ</recordid><startdate>199612</startdate><enddate>199612</enddate><creator>Venes, A.G.W.</creator><creator>van-de-Plassche, R.J.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199612</creationdate><title>An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing</title><author>Venes, A.G.W. ; van-de-Plassche, R.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c275t-1c8511099ab167622d33601109eb3c2da7126f9477f9deea8584dc09bfd9df373</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Analog-digital conversion</topic><topic>Bandwidth</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Data preprocessing</topic><topic>Frequency conversion</topic><topic>Interpolation</topic><topic>Power dissipation</topic><topic>Signal to noise ratio</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Venes, A.G.W.</creatorcontrib><creatorcontrib>van-de-Plassche, R.J.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Venes, A.G.W.</au><au>van-de-Plassche, R.J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1996-12</date><risdate>1996</risdate><volume>31</volume><issue>12</issue><spage>1846</spage><epage>1853</epage><pages>1846-1853</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.</abstract><pub>IEEE</pub><doi>10.1109/4.545804</doi><tpages>8</tpages></addata></record>
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source	IEEE Electronic Library (IEL)
subjects	Analog-digital conversion Bandwidth Clocks CMOS technology Data preprocessing Frequency conversion Interpolation Power dissipation Signal to noise ratio Voltage
title	An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
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