Modeling device and layout effects of performance driven I/sup 2/L

Modeling device and layout effects of performance driven I/sup 2/L

The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the sp...

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Veröffentlicht in:IEEE journal of solid-state circuits 1977-04, Vol.12 (2), p.155-162
Hauptverfasser: Gaffney, D.P., Bhattacharyya, A.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit simulation
Circuit testing
Delay effects
Diodes
Doping
Inverters
Logic testing
Metallization
Propagation delay
Upper bound
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Beschreibung
Zusammenfassung:The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the speed-power product curve. This paper considers these three factors with the aid of a device model, circuit simulations, and test data from logic race structures.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1977.1050865