Sub-50 nm gate length SOI transistor development for high performance microprocessors
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE) PD SOI transistors into volume manufacturing for high-speed...
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| Veröffentlicht in: | Materials science & engineering. B, Solid-state materials for advanced technology Solid-state materials for advanced technology, 2004-12, Vol.114, p.3-8 |
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| container_title | Materials science & engineering. B, Solid-state materials for advanced technology |
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| creator | Horstmann, M. Greenlaw, D. Feudel, Th Wei, A. Frohberg, K. Burbach, G. Gerhardt, M. Lenski, M. Stephan, R. Wieczorek, K. Schaller, M. Hohage, J. Ruelke, H. Klais, J. Huebler, P. Luning, S. Bentum, R. van Grasshoff, G. Schwan, C. Cheek, J. Buller, J. Krishnan, S. Raab, M. Kepler, N. |
| description | Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40
nm gate length (L
GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L
GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5
ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI. |
| doi_str_mv | 10.1016/j.mseb.2004.07.077 |
| format | Article |
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nm gate length (L
GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L
GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5
ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.</description><identifier>ISSN: 0921-5107</identifier><identifier>EISSN: 1873-4944</identifier><identifier>DOI: 10.1016/j.mseb.2004.07.077</identifier><language>eng</language><publisher>Elsevier B.V</publisher><subject>L GATE scaling ; Partial depleted SOI technologies ; Shallow trench isolation</subject><ispartof>Materials science & engineering. B, Solid-state materials for advanced technology, 2004-12, Vol.114, p.3-8</ispartof><rights>2004 Elsevier B.V.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0921510704003113$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,776,780,3536,27903,27904,65309</link.rule.ids></links><search><creatorcontrib>Horstmann, M.</creatorcontrib><creatorcontrib>Greenlaw, D.</creatorcontrib><creatorcontrib>Feudel, Th</creatorcontrib><creatorcontrib>Wei, A.</creatorcontrib><creatorcontrib>Frohberg, K.</creatorcontrib><creatorcontrib>Burbach, G.</creatorcontrib><creatorcontrib>Gerhardt, M.</creatorcontrib><creatorcontrib>Lenski, M.</creatorcontrib><creatorcontrib>Stephan, R.</creatorcontrib><creatorcontrib>Wieczorek, K.</creatorcontrib><creatorcontrib>Schaller, M.</creatorcontrib><creatorcontrib>Hohage, J.</creatorcontrib><creatorcontrib>Ruelke, H.</creatorcontrib><creatorcontrib>Klais, J.</creatorcontrib><creatorcontrib>Huebler, P.</creatorcontrib><creatorcontrib>Luning, S.</creatorcontrib><creatorcontrib>Bentum, R. van</creatorcontrib><creatorcontrib>Grasshoff, G.</creatorcontrib><creatorcontrib>Schwan, C.</creatorcontrib><creatorcontrib>Cheek, J.</creatorcontrib><creatorcontrib>Buller, J.</creatorcontrib><creatorcontrib>Krishnan, S.</creatorcontrib><creatorcontrib>Raab, M.</creatorcontrib><creatorcontrib>Kepler, N.</creatorcontrib><title>Sub-50 nm gate length SOI transistor development for high performance microprocessors</title><title>Materials science & engineering. B, Solid-state materials for advanced technology</title><description>Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40
nm gate length (L
GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L
GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5
ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.</description><subject>L GATE scaling</subject><subject>Partial depleted SOI technologies</subject><subject>Shallow trench isolation</subject><issn>0921-5107</issn><issn>1873-4944</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><recordid>eNotUMtqwzAQFKWFpml_oCederO7kvyEXkroIxDIIc1ZKPIqUbCtVJLz_VVIYWB3YNidGUKeGeQMWPV6zIeAu5wDFDnUCfUNmbGmFlnRFsUtmUHLWVYyqO_JQwhHAGCc8xnZbqZdVgIdB7pXEWmP4z4e6Ga9pNGrMdgQnacdnrF3pwHHSE3iB7s_0BP6tA9q1EgHq707eacxBOfDI7kzqg_49D_nZPv58bP4zlbrr-XifZUhF23MVNVhKRpeVNAZwwVUHZjKKMNYpxTTJbbMNFoYpiuFCqFsix2HRFJm4EzMycv1bnr9O2GIcrBBY9-rEd0UJG9E3fCmSMK3qxCTm7NFL4O2mJx31qOOsnNWMpCXLuVRXrqUly4l1Am1-AOxdGqa</recordid><startdate>20041215</startdate><enddate>20041215</enddate><creator>Horstmann, M.</creator><creator>Greenlaw, D.</creator><creator>Feudel, Th</creator><creator>Wei, A.</creator><creator>Frohberg, K.</creator><creator>Burbach, G.</creator><creator>Gerhardt, M.</creator><creator>Lenski, M.</creator><creator>Stephan, R.</creator><creator>Wieczorek, K.</creator><creator>Schaller, M.</creator><creator>Hohage, J.</creator><creator>Ruelke, H.</creator><creator>Klais, J.</creator><creator>Huebler, P.</creator><creator>Luning, S.</creator><creator>Bentum, R. van</creator><creator>Grasshoff, G.</creator><creator>Schwan, C.</creator><creator>Cheek, J.</creator><creator>Buller, J.</creator><creator>Krishnan, S.</creator><creator>Raab, M.</creator><creator>Kepler, N.</creator><general>Elsevier B.V</general><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20041215</creationdate><title>Sub-50 nm gate length SOI transistor development for high performance microprocessors</title><author>Horstmann, M. ; Greenlaw, D. ; Feudel, Th ; Wei, A. ; Frohberg, K. ; Burbach, G. ; Gerhardt, M. ; Lenski, M. ; Stephan, R. ; Wieczorek, K. ; Schaller, M. ; Hohage, J. ; Ruelke, H. ; Klais, J. ; Huebler, P. ; Luning, S. ; Bentum, R. van ; Grasshoff, G. ; Schwan, C. ; Cheek, J. ; Buller, J. ; Krishnan, S. ; Raab, M. ; Kepler, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-e239t-a6de5382460dff2306d0f6faf11daa1c5e91f8c3f1c6aeae0594b20c6a0160213</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>L GATE scaling</topic><topic>Partial depleted SOI technologies</topic><topic>Shallow trench isolation</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Horstmann, M.</creatorcontrib><creatorcontrib>Greenlaw, D.</creatorcontrib><creatorcontrib>Feudel, Th</creatorcontrib><creatorcontrib>Wei, A.</creatorcontrib><creatorcontrib>Frohberg, K.</creatorcontrib><creatorcontrib>Burbach, G.</creatorcontrib><creatorcontrib>Gerhardt, M.</creatorcontrib><creatorcontrib>Lenski, M.</creatorcontrib><creatorcontrib>Stephan, R.</creatorcontrib><creatorcontrib>Wieczorek, K.</creatorcontrib><creatorcontrib>Schaller, M.</creatorcontrib><creatorcontrib>Hohage, J.</creatorcontrib><creatorcontrib>Ruelke, H.</creatorcontrib><creatorcontrib>Klais, J.</creatorcontrib><creatorcontrib>Huebler, P.</creatorcontrib><creatorcontrib>Luning, S.</creatorcontrib><creatorcontrib>Bentum, R. van</creatorcontrib><creatorcontrib>Grasshoff, G.</creatorcontrib><creatorcontrib>Schwan, C.</creatorcontrib><creatorcontrib>Cheek, J.</creatorcontrib><creatorcontrib>Buller, J.</creatorcontrib><creatorcontrib>Krishnan, S.</creatorcontrib><creatorcontrib>Raab, M.</creatorcontrib><creatorcontrib>Kepler, N.</creatorcontrib><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Materials science & engineering. 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nm gate length (L
GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L
GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5
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| source | Elsevier ScienceDirect Journals |
| subjects | L GATE scaling Partial depleted SOI technologies Shallow trench isolation |
| title | Sub-50 nm gate length SOI transistor development for high performance microprocessors |
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